The present invention relates generally to digital systems, and more specifically, to clock/data buffer elements used in synchronous digital systems.
A clock distribution tree is a network comprising buffers, inverters and flip-flops that are connected together to provide synchronized clock signals in a synchronous digital system. In a MOSFET transistor, the input capacitance changes in response to variations in output load. More particularly, the input capacitance due to the overlap capacitance between the gate and drain of the transistor is partially reflected back to an output of preceding stage driver. The input capacitance of the buffer is proportional to the size of transistors (or output load of the buffer which in turn reflects the size of transistors). The gate-drain overlap capacitance of a MOSFET transistor is multiplied by gain and reflected at gate because of Miller Effect and known as the Miller Capacitance. Standard library cells with a small number of stages of transistors, such as inverters, buffers, and NAND gates, are most affected by Miller Effect. Hence, in a digital system design, Miller Effect is pronounced in the design of clock distribution trees, which typically consist of standard cell buffers and inverters. Miller Effect is more dominant in deep sub-micron designs such as c90 and c65 due to shrinking geometries and likely to get worse in 45 nm and beyond.
There is substantial variation in the output load and the input signal transition time of clock tree elements between the logic synthesis phase, the post-clock tree design phase, and the post-route phase of a digital system design. This unpredictable nature of Miller capacitance may cause timing mismatches between the functional design and the post-layout design of a digital system. Current digital systems avoid timing mismatches by taking into account Miller Effect during the logic synthesis phase. This is achieved by using larger drive cells than required. The use of large drive cells increases power consumption. This approach may also result in unexpected hold time failures. Another approach used to rectify timing mismatches is to manually fix the post-layout timing.
It is desirable to design buffer elements used in a clock tree that are not susceptible to Miller Effect.